1. Field of the Invention
The present invention relates to capacitor fabrication techniques applicable to dynamic random access memories (DRAMs) of highly integrated semiconductor devices, and more particularly, to capacitors of such DRAMs capable of achieving an improved degree of integration and a method for fabricating same.
2. Description of the Prior Art
Generally, a DRAM comprises a plurality of unit cells each including a capacitor for storing electric charges therein and a field effect transistor for opening and closing charging and discharging passages of the capacitor. As such, a DRAM generally has a higher degree of integration, and its DRAM cell generally has a reduced occupied area. Due to such reduction in an occupied area of a DRAM cell, it is difficult to ensure required storage capacitance. In order to inhibit such a decrease in storage capacitance caused by the reduced occupied area of the capacitor, there has been proposed a variety of methods for forming a plurality of vertical protrusions on the surface of storage electrodes, in an attempt to increase the surface area thereof. In accordance with such known methods, however, the number of vertical protrusions is considerably limited due to the reduced occupied area of memory cells. As a result, a conventional capacitor fabricated in accordance with such a method generally has insufficient storage capacitance because the storage electrode surface typically has a limited number of vertical protrusions.
FIGS. 1A to 1E are sectional views respectively illustrating a method for fabricating a conventional capacitor structure in which vertical protrusions are provided at its storage electrode.
In FIG. 1A, a silicon substrate 1 is shown, over which is formed an oxide film 2 for an element isolation, a gate oxide film 3, word lines 4 and insulating film spacers 5 in accordance with this method. Over the entire exposed surface of the silicon substrate 1, a first insulating layer 6 for planarization and a second insulating layer 7 are formed in this order. The second insulating layer 7 has a higher etch selectivity than that of the first insulating layer 6. Over the second insulating layer 7, a first polysilicon layer 8 for storage electrode and a third insulating layer 9 are sequentially formed. The first polysilicon layer 8 is connected to the surface of the silicon substrate 1 via the first and second insulating layers 6 and 7. The formation of the first polysilicon layer 8 is achieved by etching respective predetermined portions of the second insulating layer 7 and first insulating layer 6 to form a contact hole, and then thickly depositing polysilicon over the entire exposed surface of the resulting structure including the contact hole.
Thereafter, polysilicon pieces 10 are formed on the third insulating layer 9. The formation of polysilicon pieces 10 is achieved by maintaining the structure obtained after the formation of the third insulating layer 9 for a predetermined time under predetermined pressure, temperature and atmospheric conditions. For example, the conditions may be a pressure of 100 mtorr, a temperature of 580.degree. C., and an atmosphere of SiH.sub.4.
Using the polysilicon pieces 10 as a mask, the third insulating layer 9 is subsequently dry-etched at portions exposed between the polysilicon pieces 10, thereby forming a third insulating layer pattern 9A, as shown in FIG. 1B. Under a condition that the third insulating layer pattern 9A is used as a mask, the first polysilicon layer 8 is etched to a predetermined thickness at exposed portions, thereby forming a plurality of polysilicon protrusions 8A. Upon etching the first polysilicon layer 8, the polysilicon pieces 10 disposed on the third insulating layer pattern 9A are removed.
Over the entire exposed surface of the resulting structure, which is perspectively shown in FIG. 2, a fourth insulating layer 11 and a photoresist film pattern 12 are sequentially formed, as shown in FIG. 1C.
As shown in FIG. 1D, steps of forming a first polysilicon layer pattern 8B and a fourth insulating layer pattern 11A are carried out. The formation of these patterns 8B and 11A are achieved by etching the exposed portion of the fourth insulating layer 11 and respective portions of the third insulating layer pattern 9A, and the first polysilicon layer 8 disposed beneath the exposed portion of the fourth insulating layer 11 under a condition that the photoresist film pattern 12 is used as a mask. After the formation of the first polysilicon layer pattern 8B, the photoresist film pattern 12 is removed.
After completion of the steps discussed with regard to FIG. 1D, the fourth insulating layer pattern 11A, the third insulating layer pattern 9A and the second insulating layer 7 are wet-etched to be completely removed, as shown in FIG. 1E. As a result, a storage electrode, which is constituted by the first polysilicon pattern 8B and the polysilicon protrusions 8A, is exposed. Over the entire exposed surface of the storage electrode, a dielectric film 13 and a plate electrode 14 are sequentially formed, as shown in FIG. 1E. Thus, a capacitor is obtained.
FIG. 2 is a perspective view illustrating the storage electrode formed in accordance with the above-mentioned conventional method. By referring to FIG. 2, it can be found that the storage electrode includes an electrode plate constituted by the first polysilicon pattern 8B, and a plurality of vertical columns constituted by the protrusions 8A finely formed on the electrode plate.
The capacitor fabricated in accordance with the above-mentioned conventional method has an increased capacitance by virtue of its storage electrode having a structure including a plurality of finely formed vertical columns. However, since the number of vertical columns is greatly reduced due to the reduction in cell sizes, a significant amount of unexploited empty space is present along at the edge of the storage electrode. As a result, the capacitance of the capacitor is significantly limited.